TRAP SYSTEM OF SOFTWARE INSTRUCTION

PURPOSE:To deduce a software instruction by providing a mask bit for re-extraction of an instruction and to prevent the action of a designation bit for trap of an instruction analysis memory. CONSTITUTION:When an instruction trap is active, an instruction analysis memory IDM is read out in the 1st s...

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1. Verfasser: OONISHI SHIGEKI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To deduce a software instruction by providing a mask bit for re-extraction of an instruction and to prevent the action of a designation bit for trap of an instruction analysis memory. CONSTITUTION:When an instruction trap is active, an instruction analysis memory IDM is read out in the 1st step and a preprocessing routine 3 is executed in the 2nd step. Thus a mask bit is set at ''1'' and the state is analyzed before execution of an instruction to decide an exception or not. When an answer YES is obtained, a trap request bit TRPRQ is set at ''1''. Then the instruction is executed again from the 1st step. A branch is carried out to Add-0 in the 2nd step and an instruction execution routine 4 is executed. The procedure is through after a final step FOP instruction is executed. In this case, a branch is carried out to Add-2 of a post-processing routine 6 as long as the bit TRPRQ is set at ''1''. The state is analyzed after execution of an instruction to decide an exception or not. Then a branch is carried out to an exceptional processing routine or the 1st step for start of instruction according to the result of said decision.