JPS61654B

PURPOSE:To perform checking of the justness of an error detecting and correcting circuit very simply by having the data read from the same address checked by the error detecting and correcting circuit. CONSTITUTION:A check bit is formed by a check bit generating and correcting circuit 6. Next, pure...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: FUJII SHIGERU, OZAWA HIDEKYO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To perform checking of the justness of an error detecting and correcting circuit very simply by having the data read from the same address checked by the error detecting and correcting circuit. CONSTITUTION:A check bit is formed by a check bit generating and correcting circuit 6. Next, pure data and the check bit are written into a memory. A mode latch 11 is set and a signal bus l2 are selected, The pure data and the check bit are set in an input register 1, and are inputted to a syndrome bit making circuit 3. The circuit 3 makes the check bit, and compares this and the check bit applied to the read data, thereby making a syndrome.