MEMORY CONTROL DEVICE
PURPOSE:To shorten a suppressing time by installing a circuit to prohibit new registration to a line designated by a cache memory, a circuit to sweep out data of a designated line and a memory access inhibit circuit from an input output control device. CONSTITUTION:A line designation new allocation...
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| creator | OMORI YUZO |
| description | PURPOSE:To shorten a suppressing time by installing a circuit to prohibit new registration to a line designated by a cache memory, a circuit to sweep out data of a designated line and a memory access inhibit circuit from an input output control device. CONSTITUTION:A line designation new allocation prohibit bit 119 to prohibit that a line corresponding at the time of mishitting a cache memory 131 is a contrast to replacement, a sweeping-away control circuit 123 to sweep away cache memory data to a main memory device 201 of line unit by the request from a requesting party, and a sweeping-away row address counter 122 and an input output control device request reception inhibit bit 124 to inhibit a memory access to a memory control device 101 by an input output control device 401 when it is set are installed in the memory control device 101. Thus, a memory access suppressing time is shortened and a dynamic alteration processing of a system composition is improved. |
| format | Patent |
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CONSTITUTION:A line designation new allocation prohibit bit 119 to prohibit that a line corresponding at the time of mishitting a cache memory 131 is a contrast to replacement, a sweeping-away control circuit 123 to sweep away cache memory data to a main memory device 201 of line unit by the request from a requesting party, and a sweeping-away row address counter 122 and an input output control device request reception inhibit bit 124 to inhibit a memory access to a memory control device 101 by an input output control device 401 when it is set are installed in the memory control device 101. Thus, a memory access suppressing time is shortened and a dynamic alteration processing of a system composition is improved.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1986</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19860308&DB=EPODOC&CC=JP&NR=S6148053A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19860308&DB=EPODOC&CC=JP&NR=S6148053A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OMORI YUZO</creatorcontrib><title>MEMORY CONTROL DEVICE</title><description>PURPOSE:To shorten a suppressing time by installing a circuit to prohibit new registration to a line designated by a cache memory, a circuit to sweep out data of a designated line and a memory access inhibit circuit from an input output control device. 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Thus, a memory access suppressing time is shortened and a dynamic alteration processing of a system composition is improved.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1986</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBD1dfX1D4pUcPb3Cwny91FwcQ3zdHblYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxXgHBZoYmFgamxo7GRCgBAGmJHtI</recordid><startdate>19860308</startdate><enddate>19860308</enddate><creator>OMORI YUZO</creator><scope>EVB</scope></search><sort><creationdate>19860308</creationdate><title>MEMORY CONTROL DEVICE</title><author>OMORI YUZO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS6148053A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1986</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>OMORI YUZO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OMORI YUZO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY CONTROL DEVICE</title><date>1986-03-08</date><risdate>1986</risdate><abstract>PURPOSE:To shorten a suppressing time by installing a circuit to prohibit new registration to a line designated by a cache memory, a circuit to sweep out data of a designated line and a memory access inhibit circuit from an input output control device. CONSTITUTION:A line designation new allocation prohibit bit 119 to prohibit that a line corresponding at the time of mishitting a cache memory 131 is a contrast to replacement, a sweeping-away control circuit 123 to sweep away cache memory data to a main memory device 201 of line unit by the request from a requesting party, and a sweeping-away row address counter 122 and an input output control device request reception inhibit bit 124 to inhibit a memory access to a memory control device 101 by an input output control device 401 when it is set are installed in the memory control device 101. Thus, a memory access suppressing time is shortened and a dynamic alteration processing of a system composition is improved.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | MEMORY CONTROL DEVICE |
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