JPS6135638B

PURPOSE:To mask defective bits easily and surely at the comparison test time and to simplify the test, by addressing the fail memory through the address switching part provided with an address swapping part. CONSTITUTION:The address output from address pattern generator APG is caused to pass through...

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Bibliographische Detailangaben
1. Verfasser: NOZAKI SHIGEKI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To mask defective bits easily and surely at the comparison test time and to simplify the test, by addressing the fail memory through the address switching part provided with an address swapping part. CONSTITUTION:The address output from address pattern generator APG is caused to pass through address switching part AE provided with the address swapping part as it is in case of a normal address but is converted to a swap address through part AE in case of the swap mode, and this address accesses RAM to be tested and fail memory FM, where defective bit positions are stored with the high level, simultaneously. Consequently, the same corresponding address positions of RAM and memory FM are accessed independently of the mode of the address; and if the fail state is written in memory FM once, the mask operation to inhibit the comparison between the read value of RAM and the expected value in comparator CMP for defective bits is performed easily and surely even if addresses are switched thereafter.