DYNAMIC RAM

PURPOSE:To speed up further a high speed action and to improve an action margin by controlling the timing when the selection level of a word line is raised at a high level more than a power source voltage by means of a word line selection/activation circuit for consisting of a circuit similar to an address decoder. CONSTITUTION:A memory cell for storing information is constituted of an information storing capacitor and an address selecting MOSFET, and selected by an address decoder R-DCR2. Synchronizing with a selecting action, an address decoder R-DCR1 constituted of circuits similar to said decoder R-DCR2 operates as an activating circuit. With the supply of an address signal, a word line selection timing signal phix is transmitted from a node between FETs Q39 and Q40, and its voltage is raised at a high level more than a power source Vcc of the signal phix by inverter circuits 1V2-1V5 serially connected to a bootstrap CB. Thus an RAM can act at a high speed, and simultaneously its action margin can be improved.