DECODING CIRCUIT FOR PICTURE SIGNAL

PURPOSE:To shorten a processing time of decoding by providing a counter controlled so as to quickly traverse when a run length is above a prescribed value and a means for generating a binarization picture signal by the run length set in the counter. CONSTITUTION:A value of a run length is set to a c...

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description PURPOSE:To shorten a processing time of decoding by providing a counter controlled so as to quickly traverse when a run length is above a prescribed value and a means for generating a binarization picture signal by the run length set in the counter. CONSTITUTION:A value of a run length is set to a counter of 12 bits constituted by counters 21, 22, 23, and this value is subtracted by a clock supplied to a terminal 29. When the value of the counters 21, 22, 23 go to 0, an output is generated from a NAND gate 26, this output is fed to a microprogram control section MPU not shown and the generation of the binarization signal is controlled. The binarization picture image signal is generated from a binary picture signal generating circuit 30 by a command from the MPU. The output of the circuit 30 is fed to a serial.parallel conversion circuit 8 every 1 clock and fed to a buffer circuit 31 to form all the 16 bit white of black binary picture signals.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS61251370A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS61251370A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS61251370A3</originalsourceid><addsrcrecordid>eNrjZFB2cXX2d_H0c1dw9gxyDvUMUXDzD1II8HQOCQ1yVQj2dPdz9OFhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcFmhkamhsbmBo7GxKgBAFbfIuU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DECODING CIRCUIT FOR PICTURE SIGNAL</title><source>esp@cenet</source><creator>DOI TETSUO</creator><creatorcontrib>DOI TETSUO</creatorcontrib><description>PURPOSE:To shorten a processing time of decoding by providing a counter controlled so as to quickly traverse when a run length is above a prescribed value and a means for generating a binarization picture signal by the run length set in the counter. CONSTITUTION:A value of a run length is set to a counter of 12 bits constituted by counters 21, 22, 23, and this value is subtracted by a clock supplied to a terminal 29. When the value of the counters 21, 22, 23 go to 0, an output is generated from a NAND gate 26, this output is fed to a microprogram control section MPU not shown and the generation of the binarization signal is controlled. The binarization picture image signal is generated from a binary picture signal generating circuit 30 by a command from the MPU. The output of the circuit 30 is fed to a serial.parallel conversion circuit 8 every 1 clock and fed to a buffer circuit 31 to form all the 16 bit white of black binary picture signals.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><creationdate>1986</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19861108&amp;DB=EPODOC&amp;CC=JP&amp;NR=S61251370A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19861108&amp;DB=EPODOC&amp;CC=JP&amp;NR=S61251370A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DOI TETSUO</creatorcontrib><title>DECODING CIRCUIT FOR PICTURE SIGNAL</title><description>PURPOSE:To shorten a processing time of decoding by providing a counter controlled so as to quickly traverse when a run length is above a prescribed value and a means for generating a binarization picture signal by the run length set in the counter. CONSTITUTION:A value of a run length is set to a counter of 12 bits constituted by counters 21, 22, 23, and this value is subtracted by a clock supplied to a terminal 29. When the value of the counters 21, 22, 23 go to 0, an output is generated from a NAND gate 26, this output is fed to a microprogram control section MPU not shown and the generation of the binarization signal is controlled. The binarization picture image signal is generated from a binary picture signal generating circuit 30 by a command from the MPU. The output of the circuit 30 is fed to a serial.parallel conversion circuit 8 every 1 clock and fed to a buffer circuit 31 to form all the 16 bit white of black binary picture signals.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1986</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFB2cXX2d_H0c1dw9gxyDvUMUXDzD1II8HQOCQ1yVQj2dPdz9OFhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcFmhkamhsbmBo7GxKgBAFbfIuU</recordid><startdate>19861108</startdate><enddate>19861108</enddate><creator>DOI TETSUO</creator><scope>EVB</scope></search><sort><creationdate>19861108</creationdate><title>DECODING CIRCUIT FOR PICTURE SIGNAL</title><author>DOI TETSUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS61251370A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1986</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>PICTORIAL COMMUNICATION, e.g. TELEVISION</topic><toplevel>online_resources</toplevel><creatorcontrib>DOI TETSUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DOI TETSUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DECODING CIRCUIT FOR PICTURE SIGNAL</title><date>1986-11-08</date><risdate>1986</risdate><abstract>PURPOSE:To shorten a processing time of decoding by providing a counter controlled so as to quickly traverse when a run length is above a prescribed value and a means for generating a binarization picture signal by the run length set in the counter. CONSTITUTION:A value of a run length is set to a counter of 12 bits constituted by counters 21, 22, 23, and this value is subtracted by a clock supplied to a terminal 29. When the value of the counters 21, 22, 23 go to 0, an output is generated from a NAND gate 26, this output is fed to a microprogram control section MPU not shown and the generation of the binarization signal is controlled. The binarization picture image signal is generated from a binary picture signal generating circuit 30 by a command from the MPU. The output of the circuit 30 is fed to a serial.parallel conversion circuit 8 every 1 clock and fed to a buffer circuit 31 to form all the 16 bit white of black binary picture signals.</abstract><oa>free_for_read</oa></addata></record>
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subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
title DECODING CIRCUIT FOR PICTURE SIGNAL
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T16%3A45%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=DOI%20TETSUO&rft.date=1986-11-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS61251370A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true