PHASE LOCKED LOOP

PURPOSE:To remarkably shorten the time required until phase lock is established by forcedly performing initial leading-in operations by resetting a frequency dividing circuit when an asynchronous state continuously occurs over a time period longer than a certain degree of period. CONSTITUTION:A frame pulse (FP) phase comparator circuit 4 performs phase comparison between a detected FP point and the specific point of an internal FP signal which is the output of a frequency dividing circuit 12 and outputs '0', when the difference between both points is within the range of + or -1 clock. The circuit 4 outputs '1' if the difference between both points is out of the range of + or -1 clock. A discriminating circuit 13 observes the output of the FP phase comparator circuit 4 and, when '1' is continuously observed by a previously fixed number of times (for example: 8 times), outputs '1'. A reset pulse generating circuit 14 is set to a waiting state when the output of the discriminating circuit 13 changes from '0' to '1' and generates a reset pulse 15 at the timing of first arriving detected FP point. Then a loop filter 6 and frequency dividing circuits 11 and 12 are reset to prescribed initial states.