SEMICONDUCTOR MEMORY

PURPOSE:To reduce a noise level generated in a power source voltage wirings or a ground wire of a circuit by dividing two memory mats at right and left sides of an X-address decoder, and symmetrically assigning addresses to the divided memory. CONSTITUTION:Two memory mats M-ARYR, M-ARYL are disposed...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KONDO NAOHITO, NOSAKA TOSHIO, NAKAMURA HIDEAKI, KUBODERA MASAAKI, KUNITO SOUICHI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To reduce a noise level generated in a power source voltage wirings or a ground wire of a circuit by dividing two memory mats at right and left sides of an X-address decoder, and symmetrically assigning addresses to the divided memory. CONSTITUTION:Two memory mats M-ARYR, M-ARYL are disposed at right and left sides on X-address decoder XDCR as a center. The mats are divided in data line direction to form a plurality of memory arrays M0-M7. Addresses are assigned symmetrically to the memory arrays at the decoder XDCR as a center. Thus, the wiring length for connecting between the memory arrays of pairs become different according to word line length at the decoder as a center in the two mats. As a result, since a current flowed to the power source voltage line of an integrated circuit or the ground line of a circuit is averaged, a noise level can be reduced.