SIGNAL DETECTING SYSTEM

SIGNAL DETECTING SYSTEM

PURPOSE:To improve the reliability of signal transmission/reception to a random error in comparison with majority decision discrimination in the unit of block by performing majority decision in the unit of bits. CONSTITUTION:When the input of received 5-block singal to shift registers SR1-SR5 is fin...

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Hauptverfasser: KOMAGATA HITOSHI, WATABE TOSHIYUKI
Format: Patent
Sprache:eng
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ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator KOMAGATA HITOSHI
WATABE TOSHIYUKI
description PURPOSE:To improve the reliability of signal transmission/reception to a random error in comparison with majority decision discrimination in the unit of block by performing majority decision in the unit of bits. CONSTITUTION:When the input of received 5-block singal to shift registers SR1-SR5 is finished in the order of reception block from an input terminal 11 in order, the signal is outputted to a ROM 8 from the head bit of each SR and data 12 corresponding to the stored address information 10 is outputted to a Dout9. The bit of the Dout is the result of discrimination of majority decision at each 5 bits. For example, if the 1st bit of the register SR2 is 0 in error, the address information is (10111) and 1 is outputted as the D0 corresponding thereto. Then the address information of the 2nd bit the (00100) and 0 is outputted as the result of discrimination. Through the operations by five times, 3/5 bit majority decision is finished for 5-block transmission and (10101) outputted from a ROM output terminal is the result of discrimination.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS61194936A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS61194936A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS61194936A3</originalsourceid><addsrcrecordid>eNrjZBAP9nT3c_RRcHENcXUO8fRzVwiODA5x9eVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcFmhoaWJpbGZo7GxKgBAOOJH94</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SIGNAL DETECTING SYSTEM</title><source>esp@cenet</source><creator>KOMAGATA HITOSHI ; WATABE TOSHIYUKI</creator><creatorcontrib>KOMAGATA HITOSHI ; WATABE TOSHIYUKI</creatorcontrib><description>PURPOSE:To improve the reliability of signal transmission/reception to a random error in comparison with majority decision discrimination in the unit of block by performing majority decision in the unit of bits. CONSTITUTION:When the input of received 5-block singal to shift registers SR1-SR5 is finished in the order of reception block from an input terminal 11 in order, the signal is outputted to a ROM 8 from the head bit of each SR and data 12 corresponding to the stored address information 10 is outputted to a Dout9. The bit of the Dout is the result of discrimination of majority decision at each 5 bits. For example, if the 1st bit of the register SR2 is 0 in error, the address information is (10111) and 1 is outputted as the D0 corresponding thereto. Then the address information of the 2nd bit the (00100) and 0 is outputted as the result of discrimination. Through the operations by five times, 3/5 bit majority decision is finished for 5-block transmission and (10101) outputted from a ROM output terminal is the result of discrimination.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1986</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19860829&amp;DB=EPODOC&amp;CC=JP&amp;NR=S61194936A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19860829&amp;DB=EPODOC&amp;CC=JP&amp;NR=S61194936A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOMAGATA HITOSHI</creatorcontrib><creatorcontrib>WATABE TOSHIYUKI</creatorcontrib><title>SIGNAL DETECTING SYSTEM</title><description>PURPOSE:To improve the reliability of signal transmission/reception to a random error in comparison with majority decision discrimination in the unit of block by performing majority decision in the unit of bits. CONSTITUTION:When the input of received 5-block singal to shift registers SR1-SR5 is finished in the order of reception block from an input terminal 11 in order, the signal is outputted to a ROM 8 from the head bit of each SR and data 12 corresponding to the stored address information 10 is outputted to a Dout9. The bit of the Dout is the result of discrimination of majority decision at each 5 bits. For example, if the 1st bit of the register SR2 is 0 in error, the address information is (10111) and 1 is outputted as the D0 corresponding thereto. Then the address information of the 2nd bit the (00100) and 0 is outputted as the result of discrimination. Through the operations by five times, 3/5 bit majority decision is finished for 5-block transmission and (10101) outputted from a ROM output terminal is the result of discrimination.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1986</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAP9nT3c_RRcHENcXUO8fRzVwiODA5x9eVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcFmhoaWJpbGZo7GxKgBAOOJH94</recordid><startdate>19860829</startdate><enddate>19860829</enddate><creator>KOMAGATA HITOSHI</creator><creator>WATABE TOSHIYUKI</creator><scope>EVB</scope></search><sort><creationdate>19860829</creationdate><title>SIGNAL DETECTING SYSTEM</title><author>KOMAGATA HITOSHI ; WATABE TOSHIYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS61194936A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1986</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>KOMAGATA HITOSHI</creatorcontrib><creatorcontrib>WATABE TOSHIYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOMAGATA HITOSHI</au><au>WATABE TOSHIYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SIGNAL DETECTING SYSTEM</title><date>1986-08-29</date><risdate>1986</risdate><abstract>PURPOSE:To improve the reliability of signal transmission/reception to a random error in comparison with majority decision discrimination in the unit of block by performing majority decision in the unit of bits. CONSTITUTION:When the input of received 5-block singal to shift registers SR1-SR5 is finished in the order of reception block from an input terminal 11 in order, the signal is outputted to a ROM 8 from the head bit of each SR and data 12 corresponding to the stored address information 10 is outputted to a Dout9. The bit of the Dout is the result of discrimination of majority decision at each 5 bits. For example, if the 1st bit of the register SR2 is 0 in error, the address information is (10111) and 1 is outputted as the D0 corresponding thereto. Then the address information of the 2nd bit the (00100) and 0 is outputted as the result of discrimination. Through the operations by five times, 3/5 bit majority decision is finished for 5-block transmission and (10101) outputted from a ROM output terminal is the result of discrimination.</abstract><oa>free_for_read</oa></addata></record>
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subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title SIGNAL DETECTING SYSTEM
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T05%3A00%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KOMAGATA%20HITOSHI&rft.date=1986-08-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS61194936A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true