ERROR INFORMING SYSTEM

PURPOSE:To inform assuredly an error produced at a follower device of a CPU to the CPU by resetting simultaneously the CPU with an SVP, and making said device perform an error interruption with a mask. CONSTITUTION:An SVP2 resets a CHU3 to delete the factor of an error in case the error is produced within the CHU3. Then the SVP2 turns on a forcible interruption register IRTX8 and sends a forcible interruption signal to a CPU1. The CPU1 sends the stored mask data (a) on the CHU3 to the CHU3 to ask the recovery processing. Then the CHU3 sets again the mask data to a mask register MSKR5 and also sets an error interruption factor A to an interruption register IRTR4. The CHU3 gives information to the CPU1 when said setting operations are through in a normal state. An error interruption signal is sent to the CPU1 as long as the data (a) is kept on. Then the CPU1 performs the interruption processing for an error of a device and informs the error of the device to the softwave.