DIGITAL PATTERN TESTER

PURPOSE:To correct timing automatically even when a circuit delay time is different by applying a state signal regarding the internal state of a pattern control circuit to a basic clock generating circuit, and correcting the timing according to the state signal. CONSTITUTION:The state signal indicating the internal state of the pattern control circuit 10 is applied to the clock control circuit 25 of the basic clock generating circuit 20 and the control circuit 25 outputs a control signal which controls the timing correction to a clock pattern generator 27. Further, the generator 27 makes a specific timing correction according to the internal state of the pattern control circuit 10 on the basis of the control signal from the control circuit 25 and parameters from a clock definition memory 26 and then outputs a rate signal to a memory address control circuit 14. Further, a signal F-CLK is outputted to a format circuit 34 and a signal STRB is outputted to a comparator 31. Consequently, a tester having the basic clock generating circuit 20 which makes the timing correction automatically is obtained.