SCAN SYSTEM OF INFORMATION PROCESSOR

PURPOSE:To decrease greatly the number of logical gates of scan-in by reading out the contents of a data memory element, and setting data to be set to a one bit data memory element to which the data is to be scanned in. CONSTITUTION:In case of the scan-in, data of a one bit information unit, includi...

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Bibliographische Detailangaben
1. Verfasser:	WAKAI KATSURO
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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Beschreibung
Zusammenfassung:	PURPOSE:To decrease greatly the number of logical gates of scan-in by reading out the contents of a data memory element, and setting data to be set to a one bit data memory element to which the data is to be scanned in. CONSTITUTION:In case of the scan-in, data of a one bit information unit, including FFs 401-0-401-7 which are scan-in objects to be indicated by a physical scan-in address, is once scanned out. One bit scan data is merged to it, and the FFs 401-0-401-7 of this information unit are set all together, and then the data equivalent to the information unit are scanned in. Only one bit changes as a result, and the purpose can be attained by scan logics of two gates per FF, namely, AND gates 404 and 405. Accordingly, tens of thousands of logical gates can be reduced in the information processors as a whole.