CHIP CARRIER

PURPOSE:To enable chip carriers to be packaged in a high density, by providing two or more wire bonding layers and arranging sealing layers stepwise in upper and lower stages so as to decrease the carrying area of the carrier. CONSTITUTION:A chip carrier 10 is provided with a die pad 11, with two wire bonding layers 12 and 13 and with sealing layers 14 and 15 which are arranged stepwise in the upper and lower stages. The bonding layers 12 and 13 are provided with a plurality of wire bonding pads 16 and 17, respectively, while the sealing layers 14 and 15 are provided with sealing pads 18 and 19, respectively. IC's 21 and 31 are received in the carrier 20 thus constructed and the carrier is sealed with a cap 35 while a sealing cap 26 is used as a die pad for the IC 31. In this manner, a plurality of IC's can be packaged three-dimentionally without increasing the carrying area of the carrier. Accordingly, such chip carriers can be packaged on a printed-circuit board in a high density.