MICROPROCESSOR

PURPOSE:To eliminate the delay time for production of a waiting signal by attaining the control of the memory cycle length within a processor when accesses are given to external memories having different speeds in response to each address space. CONSTITUTION:The external memories 101-103 having different speeds in response to each address space are connected to an address bus 104 and a data bus 105 of a microprocessor (MPU) 100. When an address signal is set to a memory address register 1 from an instruction arithmetic control part 5, an address space deciding part 2 compares the address of the register 1 with address space registers 10, 20 and 30 respectively. Then the memory cycle extension values are sent to a timing control part 3 from cycle length registers 11, 21 and 31 corresponding to each coincident space. Thus timing signals 8 and 9 corresponding to the external memories to receive accesses are outputted.