PROCESSOR CONTROL SYSTEM

PURPOSE:To attain quickly and assuredly the mechanical control of a processor by separating a control packet buffer from a general packet and giving a processor number for control packet as well as a normal processor number to each processor. CONSTITUTION:The control information sent from a master processor 3 is converted into a control packet having an address processor number added to a header within a transmission bus interface circuit 2 through a control line 5. When a bus is allocated by a system bus allocating circuit 1, the transmission is started for the information. Then the information is given to a reception register 15 and a control packet reception register 17 in a reception bus interface circuit 6. Then an address coincidence circuit 16 is actuated together with a control packet address coincidence circuit 18. Then only the circuit 18 detects the coincidence to start a DMA control circuit 19 and transfers the coincidence to a control packet buffer 20. When this transfer is finished, a microprocessor 8 reads a command code and uses a control line 9 to control a slave processor 11.