MANUFACTURE OF SEMICONDUCTOR DEVICE

PURPOSE:To prevent the lowering of dielectric withstand voltage of a gate oxide film by a method wherein a low temperature preparatory heat treatment is performed before a high temperature heat treatment is performed on a double-layer gate. CONSTITUTION:A polycrystalline Si film 3 is formed on the s...

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Bibliographische Detailangaben
Hauptverfasser: SHINOHARA SHIYOUHEI, KUGIMIYA KOUICHI, OKADA SHIYOUZOU, FUKUMOTO MASANORI, YASUI JIYUUROU
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To prevent the lowering of dielectric withstand voltage of a gate oxide film by a method wherein a low temperature preparatory heat treatment is performed before a high temperature heat treatment is performed on a double-layer gate. CONSTITUTION:A polycrystalline Si film 3 is formed on the surface of a semiconductor substrate 1 having a gate oxide film 2 and an SiO2 film 8, phosphorus is diffused into the Si film subsequently, and then an MoSi2 film 4 is vapor- deposited thereon. Then, a dry etching is performed on double-layer films 3 and 4, and a gate electrode and a wiring are formed. Subsequently, after preparatory heat treatment has been performed at approximately 600 deg.C for 30min or thereabout in N2 or N2+H2, a high temperature heat treatment is performed at approximately 1,000 deg.C for 30min of thereabout, and the wiring resistance of the double-layer film is lowered. Subsequently, a source and drain region is formed by injecting impurities using the gate electrode of the double-layer film as a mask, and an Al/Si electrode is provided. Then, by performing two stages of heat treatments of low and high temperature, the yield rate of dielectric withstand voltae of the gate oxid film can be improved.