BINARY STATE MONITOR SYSTEM

PURPOSE:To reduce the number of signal line of a binary state and display concentrically the condition of numerous monitor points at one point so as to make a monitor system more efficient by performing simple multiplexing by means of a digital circuit when an object to be monitored obtains the binary state. CONSTITUTION:By means of the bus composed of three lines of the alarm of (N+1) sets of devices DV0-DVN, a monitor is performed by displaying concentrically at one monitor part SUP. A synchronizing signal SY serves as a reset signal at each preset counter CTR, and the counting of a clock signal is started at the rise of the signal SY at an entire CRT. A binary alarm condition output AM from the NAND circuit NAG of each device DV0-DVN is arranged one by one in an AML after it is time division multiplexed and fed to the monitor section SUP where it is spatially rearranged in the output Q0-QN of a shift register SFR by the register SFR and inputted into the corresponding terminal of an FF. The output Q0-QN of the FF is fed to display devices AL0-ALN.