JPS6042634B

A continuous gate electrode overlies the channel of the CCD and is connected to a uniphase clock pulse source for operation of the CCD. Pairs of gate conductor-insulator-semiconductor regions are defined along the channel. In each pair of regions the surface potential-gate voltage characteristic of one region intersects that of the other region, such that in the OFF condition of a clock pulse the potential well at one region of each pair is deeper than that of the other region; in the ON condition of a clock pulse, this situation is reversed. In this manner, charge packets are propagated along the channel and unidirectionality is achieved by locally implanted potential wells or potential barriers in each of the aforesaid regions. The shift in surface potential gate voltage of one of the regions in each pair of regions, to produce the required intersection, is achieved by an implanted charge accumulation layer at the insulator-semiconductor interface at those regions which, in one embodiment, are defined at locally thickened areas of the insulating layer, so that the threshold voltage is greater than an intermediate regions at which the insulator layer is thinner. In a preferred embodiment, using a uniform thickness insulating layer, the threshold voltage difference is achieved by use of local, heavily doped semiconductor regions spaced along the channel with charge accumulation layers formed at the interface between those regions and the insulating layer. Fabrication techniques employing ion implantation are described for both embodiments.