JPS6041380B

PURPOSE:To increase the processing efficiency of a CPU, by storing address information and write-in data at a storage control section and making retrial of memory write-in at a storage control section, when an error is detected from the storage device. CONSTITUTION:When a write-in request of 0 side...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: NODA KATSUNOBU
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To increase the processing efficiency of a CPU, by storing address information and write-in data at a storage control section and making retrial of memory write-in at a storage control section, when an error is detected from the storage device. CONSTITUTION:When a write-in request of 0 side CPU is received, address information, write-in data, and byte mark information are stored in registers 5-6, 6-0, 7-0 of a storage control section 2. In case of full-write, the address information and the write-start signal of a write-in data register 5-0 adding the data of the register 6-0 with the error correction code are transmitted to a memory device 1, where it is written in a memory array 12. When an error is detected in the device 1 and a correctable error is detected at the control section 2 with partial-write, a control circuit 4 uses stored information and data for re-write processing.