ACCESS CONTROL SYSTEM FOR LOCAL MEMORY OF MULTIPROCESSOR SYSTEM

PURPOSE:To facilitate an analysis of the cause of abnormality and restoration by allowing each processor to mask a local memory against accessing from another processor while operating normally with the local memory, release the masking when abnormality occurs, and serve as another processor. CONSTI...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: HIRAMATSU JIYUNICHI, SUZUKI SHIGEO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator HIRAMATSU JIYUNICHI
SUZUKI SHIGEO
description PURPOSE:To facilitate an analysis of the cause of abnormality and restoration by allowing each processor to mask a local memory against accessing from another processor while operating normally with the local memory, release the masking when abnormality occurs, and serve as another processor. CONSTITUTION:When accessing to the local memory 4 by other processors is inhibited, the output of an inhibition signal generating circuit goes down to a level L, and the output of an AND circuit 15 also goes down to L to turn off transmission gates 12 and 13. At the same time, the output of an AND circuit 14 also goes down to L, and that is reported to other processors through a bus 2. If a processor 1 generates an abnormality, a control circuit 3 input H to an OR circuit 50, which outputs H regardless of the output of the inhibition signal generating circuit 40. The AND circuits 14 and 15 and transmission gates 12 and 13 are inverted into states of accessing from other processors. Thus, malfunction is prevented and the processor serves as other processors to facilitate an analysis of the abnormality and restoration.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS6029856A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS6029856A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS6029856A3</originalsourceid><addsrcrecordid>eNrjZLB3dHZ2DQ5WcPb3Cwny91EIjgwOcfVVcPMPUvDxd3b0UfB19fUPilTwd1PwDfUJ8QwI8gepB0pDVPIwsKYl5hSn8kJpbgYFN9cQZw_d1IL8-NTigsTk1LzUknivgGAzAyNLC1MzR2MilAAAZUQqzA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ACCESS CONTROL SYSTEM FOR LOCAL MEMORY OF MULTIPROCESSOR SYSTEM</title><source>esp@cenet</source><creator>HIRAMATSU JIYUNICHI ; SUZUKI SHIGEO</creator><creatorcontrib>HIRAMATSU JIYUNICHI ; SUZUKI SHIGEO</creatorcontrib><description>PURPOSE:To facilitate an analysis of the cause of abnormality and restoration by allowing each processor to mask a local memory against accessing from another processor while operating normally with the local memory, release the masking when abnormality occurs, and serve as another processor. CONSTITUTION:When accessing to the local memory 4 by other processors is inhibited, the output of an inhibition signal generating circuit goes down to a level L, and the output of an AND circuit 15 also goes down to L to turn off transmission gates 12 and 13. At the same time, the output of an AND circuit 14 also goes down to L, and that is reported to other processors through a bus 2. If a processor 1 generates an abnormality, a control circuit 3 input H to an OR circuit 50, which outputs H regardless of the output of the inhibition signal generating circuit 40. The AND circuits 14 and 15 and transmission gates 12 and 13 are inverted into states of accessing from other processors. Thus, malfunction is prevented and the processor serves as other processors to facilitate an analysis of the abnormality and restoration.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1985</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19850215&amp;DB=EPODOC&amp;CC=JP&amp;NR=S6029856A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19850215&amp;DB=EPODOC&amp;CC=JP&amp;NR=S6029856A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIRAMATSU JIYUNICHI</creatorcontrib><creatorcontrib>SUZUKI SHIGEO</creatorcontrib><title>ACCESS CONTROL SYSTEM FOR LOCAL MEMORY OF MULTIPROCESSOR SYSTEM</title><description>PURPOSE:To facilitate an analysis of the cause of abnormality and restoration by allowing each processor to mask a local memory against accessing from another processor while operating normally with the local memory, release the masking when abnormality occurs, and serve as another processor. CONSTITUTION:When accessing to the local memory 4 by other processors is inhibited, the output of an inhibition signal generating circuit goes down to a level L, and the output of an AND circuit 15 also goes down to L to turn off transmission gates 12 and 13. At the same time, the output of an AND circuit 14 also goes down to L, and that is reported to other processors through a bus 2. If a processor 1 generates an abnormality, a control circuit 3 input H to an OR circuit 50, which outputs H regardless of the output of the inhibition signal generating circuit 40. The AND circuits 14 and 15 and transmission gates 12 and 13 are inverted into states of accessing from other processors. Thus, malfunction is prevented and the processor serves as other processors to facilitate an analysis of the abnormality and restoration.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1985</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB3dHZ2DQ5WcPb3Cwny91EIjgwOcfVVcPMPUvDxd3b0UfB19fUPilTwd1PwDfUJ8QwI8gepB0pDVPIwsKYl5hSn8kJpbgYFN9cQZw_d1IL8-NTigsTk1LzUknivgGAzAyNLC1MzR2MilAAAZUQqzA</recordid><startdate>19850215</startdate><enddate>19850215</enddate><creator>HIRAMATSU JIYUNICHI</creator><creator>SUZUKI SHIGEO</creator><scope>EVB</scope></search><sort><creationdate>19850215</creationdate><title>ACCESS CONTROL SYSTEM FOR LOCAL MEMORY OF MULTIPROCESSOR SYSTEM</title><author>HIRAMATSU JIYUNICHI ; SUZUKI SHIGEO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS6029856A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1985</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>HIRAMATSU JIYUNICHI</creatorcontrib><creatorcontrib>SUZUKI SHIGEO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HIRAMATSU JIYUNICHI</au><au>SUZUKI SHIGEO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ACCESS CONTROL SYSTEM FOR LOCAL MEMORY OF MULTIPROCESSOR SYSTEM</title><date>1985-02-15</date><risdate>1985</risdate><abstract>PURPOSE:To facilitate an analysis of the cause of abnormality and restoration by allowing each processor to mask a local memory against accessing from another processor while operating normally with the local memory, release the masking when abnormality occurs, and serve as another processor. CONSTITUTION:When accessing to the local memory 4 by other processors is inhibited, the output of an inhibition signal generating circuit goes down to a level L, and the output of an AND circuit 15 also goes down to L to turn off transmission gates 12 and 13. At the same time, the output of an AND circuit 14 also goes down to L, and that is reported to other processors through a bus 2. If a processor 1 generates an abnormality, a control circuit 3 input H to an OR circuit 50, which outputs H regardless of the output of the inhibition signal generating circuit 40. The AND circuits 14 and 15 and transmission gates 12 and 13 are inverted into states of accessing from other processors. Thus, malfunction is prevented and the processor serves as other processors to facilitate an analysis of the abnormality and restoration.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPS6029856A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title ACCESS CONTROL SYSTEM FOR LOCAL MEMORY OF MULTIPROCESSOR SYSTEM
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T14%3A39%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HIRAMATSU%20JIYUNICHI&rft.date=1985-02-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS6029856A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true