ACCESS CONTROL SYSTEM FOR LOCAL MEMORY OF MULTIPROCESSOR SYSTEM
PURPOSE:To facilitate an analysis of the cause of abnormality and restoration by allowing each processor to mask a local memory against accessing from another processor while operating normally with the local memory, release the masking when abnormality occurs, and serve as another processor. CONSTI...
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creator | HIRAMATSU JIYUNICHI SUZUKI SHIGEO |
description | PURPOSE:To facilitate an analysis of the cause of abnormality and restoration by allowing each processor to mask a local memory against accessing from another processor while operating normally with the local memory, release the masking when abnormality occurs, and serve as another processor. CONSTITUTION:When accessing to the local memory 4 by other processors is inhibited, the output of an inhibition signal generating circuit goes down to a level L, and the output of an AND circuit 15 also goes down to L to turn off transmission gates 12 and 13. At the same time, the output of an AND circuit 14 also goes down to L, and that is reported to other processors through a bus 2. If a processor 1 generates an abnormality, a control circuit 3 input H to an OR circuit 50, which outputs H regardless of the output of the inhibition signal generating circuit 40. The AND circuits 14 and 15 and transmission gates 12 and 13 are inverted into states of accessing from other processors. Thus, malfunction is prevented and the processor serves as other processors to facilitate an analysis of the abnormality and restoration. |
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CONSTITUTION:When accessing to the local memory 4 by other processors is inhibited, the output of an inhibition signal generating circuit goes down to a level L, and the output of an AND circuit 15 also goes down to L to turn off transmission gates 12 and 13. At the same time, the output of an AND circuit 14 also goes down to L, and that is reported to other processors through a bus 2. If a processor 1 generates an abnormality, a control circuit 3 input H to an OR circuit 50, which outputs H regardless of the output of the inhibition signal generating circuit 40. The AND circuits 14 and 15 and transmission gates 12 and 13 are inverted into states of accessing from other processors. Thus, malfunction is prevented and the processor serves as other processors to facilitate an analysis of the abnormality and restoration.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1985</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19850215&DB=EPODOC&CC=JP&NR=S6029856A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19850215&DB=EPODOC&CC=JP&NR=S6029856A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIRAMATSU JIYUNICHI</creatorcontrib><creatorcontrib>SUZUKI SHIGEO</creatorcontrib><title>ACCESS CONTROL SYSTEM FOR LOCAL MEMORY OF MULTIPROCESSOR SYSTEM</title><description>PURPOSE:To facilitate an analysis of the cause of abnormality and restoration by allowing each processor to mask a local memory against accessing from another processor while operating normally with the local memory, release the masking when abnormality occurs, and serve as another processor. CONSTITUTION:When accessing to the local memory 4 by other processors is inhibited, the output of an inhibition signal generating circuit goes down to a level L, and the output of an AND circuit 15 also goes down to L to turn off transmission gates 12 and 13. At the same time, the output of an AND circuit 14 also goes down to L, and that is reported to other processors through a bus 2. If a processor 1 generates an abnormality, a control circuit 3 input H to an OR circuit 50, which outputs H regardless of the output of the inhibition signal generating circuit 40. The AND circuits 14 and 15 and transmission gates 12 and 13 are inverted into states of accessing from other processors. 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CONSTITUTION:When accessing to the local memory 4 by other processors is inhibited, the output of an inhibition signal generating circuit goes down to a level L, and the output of an AND circuit 15 also goes down to L to turn off transmission gates 12 and 13. At the same time, the output of an AND circuit 14 also goes down to L, and that is reported to other processors through a bus 2. If a processor 1 generates an abnormality, a control circuit 3 input H to an OR circuit 50, which outputs H regardless of the output of the inhibition signal generating circuit 40. The AND circuits 14 and 15 and transmission gates 12 and 13 are inverted into states of accessing from other processors. Thus, malfunction is prevented and the processor serves as other processors to facilitate an analysis of the abnormality and restoration.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | ACCESS CONTROL SYSTEM FOR LOCAL MEMORY OF MULTIPROCESSOR SYSTEM |
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