KEY MATRIX CIRCUIT

PURPOSE:To eliminate the reduction of the noise margin for the lock key detection level by connecting a lock key to a key matrix circuit via a three-state buffer. CONSTITUTION:Enable terminals EN1-3 of three-state buffer gates G1-3 are connected a row R1 in a key matrix circuit which can store a lock key. Thus a current flows to the R1 from a plus voltage source VH via a resistance P4 when the R1 is designated and a lock key SR1 is closed. Thus the voltages of terminals EN1-3 are set at VR1, and gates G1-3 are all opened. Therefore the voltage VD0 of a data line D0 is equal to the output voltage of logic ''0'' level of the gate G1. This never reduces the detection noise margins of lock keys SR1-3, and these keys can be stored into the key matrix circuit.