INTERMEDIATE BUFFERING SYSTEM OF COMMUNICATION PROCESSING SYSTEM

PURPOSE:To improve the throughout of a storage system by providing a common buffer memory between circuit correspondence parts and a file memory. CONSTITUTION:A common buffer memory 5 is provided between circuit correspondence parts 1-1-1-m and a file memory 3. The parts 1-1-1-m contain n-face buffe...

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Bibliographische Detailangaben
Hauptverfasser: ADACHI FUMIO, OOMURA HIROYUKI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To improve the throughout of a storage system by providing a common buffer memory between circuit correspondence parts and a file memory. CONSTITUTION:A common buffer memory 5 is provided between circuit correspondence parts 1-1-1-m and a file memory 3. The parts 1-1-1-m contain n-face buffer memories 2-1-2-n respectively and buffer data successively to transfer these data to a terminal connected to the memory 5 or either one of circuits a1-am. The transfer request given from the part 1-1 is immediately accepted by the memory 5 as long as the memory 5 has an idle area. While the queuing occurs at memories 2-1-2-n if the memory 5 is filled fully.