MULTIPROCESSOR SYSTEM

PURPOSE:To perform the fail safe processing easily without requiring backup software or special hardware by providing a means which performs the fail safe processing of a common area corresponding to a broken-down processor. CONSTITUTION:If a processor CPU10A is broken down, a processor down signal...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KIYOMOTO YUKARI, YAMANAKA KIMIO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To perform the fail safe processing easily without requiring backup software or special hardware by providing a means which performs the fail safe processing of a common area corresponding to a broken-down processor. CONSTITUTION:If a processor CPU10A is broken down, a processor down signal DWN61A is sent from this processor CPU10A to a fail safe processing device 60. The fail safe processing device 60 detects the address of the common area, which the processor CPU10A occupies, through a table 43 of a common area management device 3. The processing device 6 sends a switching signal 62 to switch a selector 64 and sends a fail safe processing signal 63 to a common bus 45 through the selector 64. The common area which the processor CPU10A occupies is subjected to he fail safe processing such as output reset, required switching to a state, for example, the system safe-side state, or the like.