GENERATOR OF MEMORY CONTROL SIGNAL

PURPOSE:To produce easily a control signal for driving a DRAM by performing the logical processing between row and column address gate signals as well as row and column address signals respectively. CONSTITUTION:The row address signal produced by a row address signal generating circuit 14 is supplied to an AND circuit 16 together with the row address gate signal RG. While the column address signal given from a column address signal generating circuit 15 is supplied to an AND circuit 17 together with the column address gate signal CG. The outputs of circuits 16 and 17 are supplied to an OR circuit 18, and an address signal is obtained from the circuit 18.