MULTIPROCESSOR SYSTEM

PURPOSE:To allow plural arithmetic processors to perform processing simultaneously without providing any common memory by providing every arithmetic processor with an individual command information storage means and also providing a common signal line. CONSTITUTION:A system controller 1 selects a corresponding address in the address space of a common bus 4 assigned to the common information storage register 8a in an arithmetic processor 10a and writes start command data for the processor 10a. Further, command data for other arithmetic processors are written on respective command information storage registers similarly. When all data are written, the controller sends a signal showing the completion of the data writing to respective processing parts 9a-9n through the common signal line 11. Consequently, interruption program processing operations of the respective arithmetic processors 10a-10n are basically the same. Namely, the plural arithmetic processors are allowed to perform processing simultaneously without providing any common memory.