TEST PATTERN GENERATING METHOD AND DEVICE FOR LSI TESTER

PURPOSE:To generate a test pattern at a high speed without reducing the number of output pins by multiplexing and outputting test pattern data and auxiliary test data. CONSTITUTION:A memory A for storing test pattern data, an auxiliary memory B for storing auxiliary test data, and multiplexers MPX1-...

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Bibliographische Detailangaben
1. Verfasser: ISHIKAWA MITSUAKI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To generate a test pattern at a high speed without reducing the number of output pins by multiplexing and outputting test pattern data and auxiliary test data. CONSTITUTION:A memory A for storing test pattern data, an auxiliary memory B for storing auxiliary test data, and multiplexers MPX1-MPXm for multiplexing the test pattern data and the auxiliary test data are provided, and a selector for selecting the arbitrary auxiliary test data from the auxiliary memory or a converter 5W for converting whether multiplexing with the auxiliary test data or not are provided. A switch PSM provided between the memory B and the multiplexers MPX1-MPXm can connect the auxiliary memory units b1-bm of the memory B with the arbitrary multiplexers MPX1-MPXm. Accordingly, even if the number of the units b1-bm of the memory B is less than that of the output pins P1-Pm, only the necessary output pins can be multiplexed with the auxiliary memory by switches SW, PSW.