CIRCUIT FOR DETECTING CENTRAL VALUE OF TIMEWISE VARIED SIGNAL

PURPOSE:To facilitate the formation of IC and accelerate the speed of response to the central value level of an input signal, by inputting the output of an A/D converter and that of a T-sec delay device to a specific comparator and inputting said outputs to the comparator through an integrator while delaying the same over one clock period. CONSTITUTION:An analogue input signal r(t) is inputted to a comparator 13 through an A/D converter 2 and the output thereof is inputted to the comparator 13 through an integrator 4 while delayed over one clock period by a T-sec delay device 10. At this time, in this comparator 13, the output of the subtractor 6 connected to the converter 2 and the delay device 10 is compared with constant values A, -B by a judge circuit 22 to be inputted to a selection circuit 23 while the output of the subtractor 6 is inputted to an sgn circuit 7 to judge the polarity thereof and multiplied by constant E to be inputted to the circuit 23. Further, the output of the subtractor 6 receives the subtraction of the constant value A and is multiplied by constant (a) and receives the addition of the constant E to be inputted circuit 23 while receives the addition of the constant value B and is multiplied by constant (b) and receives the subtraction of the constant E to be inputted to the circuit 23 and signals are taken out from the circuit 23 through the integrator 4.