SUPERCONDUCTION LOGIC CIRCUIT

PURPOSE:To obtain an NOT logic at an output of a Josephson OR circuit by providing a clock generating circuit comprising the Josephson OR circuit and an NOT circuit and a delay circuit where NOT circuits are connected in series. CONSTITUTION:The clock generating circuit 11 in which the Josephson JSP OR circuit 12 using an AC bias current B1 taking binary logic 1, 2 and the JSP NOT circuit 13 using an AC bias current B2 having a prescribed phase difference with a current source B1 are connected as a ring and outputtig a clock CP11 going to logical 1 once every time the current B2 goes to logical 1 twice, is provided. When the CP11 is inputted to a delay circuit 14 in which the JSP NOT circuit 15 using the current B1 and the JSP NOT circuit 16 using the current B2 are connected in series so as to obtain a clock CP14. The CP11 is given to an AND 22 comprising the JSP element to which the signal 20 is inputted, a latch 22 and a logical operation circuit 23 and the outputs S23, CP14 are given similarly to an ANd 24, a latch 25 and a logical operation circuit 25 so as to output an NOT logic as signals S23, S26.