MANUFACTURE OF SEMICONDUCTOR DEVICE WITH HIGH WITHSTAND VOLTAGE

PURPOSE:To simplify the process by a method wherein, when p regions of a p- channel transistor of a CMOS semiconductor device is formed, the p regions are implanted with ion without masking n-channel transistor regions. CONSTITUTION:Oxide films 3 for separating elements, n diffusion layers 5 for pre...

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Bibliographische Detailangaben
Hauptverfasser: WARITA YOSHIHIKO, AOKI TAKAO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To simplify the process by a method wherein, when p regions of a p- channel transistor of a CMOS semiconductor device is formed, the p regions are implanted with ion without masking n-channel transistor regions. CONSTITUTION:Oxide films 3 for separating elements, n diffusion layers 5 for preventig an inversion and p diffusion layers 6 are formed on the surface of an n type semiconductor substrate 1 and then a p-well 2 and thermal oxide films 4 as well as a gate electrode 7 of an n-channel transistor and another gate electrode 10 of a p-channel transistor are further formed. Then oxide films 22 are formed on an n region 8 to be a source drain and another n region 9 to be a substrate contact. After implanting with ion, p regions 21 with low impurity concentration is formed in the p-channel transistor forming region utilizing the gate electrodes 7, 10 and the oxide films 3 as masks. The depth of the p regions 21 shall not exceed that of the n regions 8, 9. The characteristics of the n regions 8, 9 may be kept unchanged since the oxide films 22 are thicker than the thermal oxide films 4.