JPS6012720B

A digital CCD arrangement is provided in which an output signal is emitted which is regenerated with respect to its voltage range, and is substantially insensitive to adverse influences. In this arrangement, the last shift electrode preceding the output end zone is coupled with respect to potential to a circuit point of a transistor stage, which point in the event of a quantity of charge carriers representing logic level "1," the output end zone experiences a change in potential which corresponds to the change in potential beneath the other shift electrodes. Between the last preceding shift electrode and the output end zone, there is arranged a further electrode which is insulated from the semiconductor layer and is connected to a second reference potential which corresponds to an intermediate value which is swept over by the potential across the circuit point.