DYNAMIC RAM

PURPOSE:To improve the operating margin by operating selectively an MOSFET provided between complementary data line pairs and a power supply voltage terminal to attain active restorage operation. CONSTITUTION:Storage information of a memory cell is read to the complementary data lines DL, -DL and the level of a timing signal phi2 is decreased, then an MOSFETQ4 connected to the data line -DL brought into a low level keeps the ON state and an MOSFETQ16 is turned off. When an active restorage control signal phi reaches a high level boosted to the power voltage VCC or over, the level is given to a gate of an MOSFETQ1 through an MOSFETQ15, the Q1 is turned on so as to restore the level of the data line DL to a high level like the power voltage VCC. Since the signal phi1 is not given to the gate of an MOSFET Q3, the Q3 remains turned off. The flowing of the current from the power supply voltage terminal to the data line -DL is prevented. The leading of the low level is increased and the sensitivity is improved.