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PURPOSE:To enable to perform a high speed operation by forming a V-shaped groove on a semiconductor layer and shortening the gate length. CONSTITUTION:A semiconductor layer 21 made of GaAs having small electron affinity, a semiconductor layer 22 having high specific resistance and large electron aff...

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Bibliographische Detailangaben
Hauptverfasser: TSUBAKI KOUTAROU, OE KUNISHIGE, KUMABE KENJI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To enable to perform a high speed operation by forming a V-shaped groove on a semiconductor layer and shortening the gate length. CONSTITUTION:A semiconductor layer 21 made of GaAs having small electron affinity, a semiconductor layer 22 having high specific resistance and large electron affinity as well as made of GaAs, and a semiconductor layer 23 having low specific resistance and small electron affinity as well as made of GaAs are laminated. A semiconductor layer 26 having high specific resistance and small electron affinity as well as made of AlGaAs is formed on a groove 25 which is formed on a laminate 24. A semiconductor layer 27 having low specific resistance and small electron affinity as well as made of AlGaAs is formed on the layer 26. A gate electrode 28 which is extended oppositely to the side surface which faces the groove 25 is attached onto the layer 27 to form a Schottky junction 29.