TESTING DEVICE FOR LOGICAL CIRCUIT

PURPOSE:To prevent the conflict between an output data of a logical circuit to be tested and an input data to the logical circuit of a testing device by providing a logical means which turns off the gate of the testing device when the output enable signal of the logical circuit to be tested has a lo...

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Bibliographische Detailangaben
1. Verfasser: YOSHIMOTO SATORU
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To prevent the conflict between an output data of a logical circuit to be tested and an input data to the logical circuit of a testing device by providing a logical means which turns off the gate of the testing device when the output enable signal of the logical circuit to be tested has a logical level ''1''. CONSTITUTION:When the output enable signal is set to logic ''0'', the output terminal of an inverter 7 is at the logical level ''1'', so an AND gate 8 turns on when the contents of a driver enable register 2 show logic ''1'' to turn on a gate 6. When the output enable signal is set to logic ''1'', namely, when the input/output buffer 1 of the logical circuit is controlled to an output state, the output terminal of the inverter 7 is at the logical level ''0'', so the AND gate 8 turns off, so that the gate 6 is never turned on. Consequently, this simple circuit constitution prevents the conflict between the outputs of the testing device and logical circuit each other.