TESTING DEVICE USING SAMPLING UNIT OPERATED AT LOW TEMPERAT-URE

This test apparatus permist the testing of high speed semiconductor devices (room-temperature chips) by a Josephson junction sampling device (cryogenic chip) without intolerable loss of resolution. The interface comprises a quartz pass-through plug which includes a planar transmission line (5) interconnecting a first chip station, where the semiconductor chip (2) to be tested is temporarily mounted and a second chip station, where the cryogenic chip (1) is mounted. The pass-through plug has a long half-cylindrical protion (3) and short half-cylindrical portion (4). The long portion carries the planar transmission line, the ends of which form the first and second chip mounting stations. The short portion completes the cylinder with the long portion for part of its length, where a seal (6) can be achieved, but does not extend over the chip mounting stations. Sealing is by epoxy cement. The pass-through plug is sealed in place in a flange mounted to the chamber wall. The first chip station is in the room temperature environment required for semiconductor operation. The second chip station, with the cryogenic chip attached, extends into a liquid helium reservoir. Proper semiconductor operating temperature is achieved by a heater wire (8) and control thermocouple (9) in the vicinity of each other and the second chip mounting station. Thermal isolation is maintained by vacuum and seals. Connections for power and control, for test result signals, for temperature control and heating, and for vacuum complete the test apparatus.