SEMICONDUCTOR MEMORY

PURPOSE:To offer a static type semiconductor memory strong in a software error by impressing a voltage higher than that of a power supply voltage to a memory cell with a boosting circuit of on-chip when a power supply voltage impressed externally with a battery backup is decreased less than that at...

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1. Verfasser: FURUYAMA TOORU
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To offer a static type semiconductor memory strong in a software error by impressing a voltage higher than that of a power supply voltage to a memory cell with a boosting circuit of on-chip when a power supply voltage impressed externally with a battery backup is decreased less than that at normal operation to increase the amount of charge at a storage node. CONSTITUTION:Taking the output amplitude of an oscillator 11 as Vcc, its frequency as (f), capacitance of a capacitor as C, and node parasitic capacitance between power supplies Vcc and V'cc as Cp, then the V'cc is increased idealistically to a value of V'ccmax=Vcc-2VT+(C/C+Cp) Vcc, independently of the frequency (f). Suppose that the Cp is sufficiently smaller than the C, said Formula becomes V'ccmax=2(Vcc-VT), where the VT is the threshold voltage of MOS transistors 8, 9, and the Vcc=2.5V and the VT=0.5V, are taken to obtain V'ccmax=4V, and on the other hand, Vcc=3V, is taken to obtain Vccmax=5V, and the same voltage as the Vcc at the normal operator is obtained.