MEMORY ADDRESS EXTENSION SYSTEM OF MICROPROCESSOR SYSTEM

MEMORY ADDRESS EXTENSION SYSTEM OF MICROPROCESSOR SYSTEM

PURPOSE:To extend memory addresses by using independently part or the whole of a data signal or in combination with an address signal as a new address signal and accessing a memory. CONSTITUTION:When an I/O signal Sio and a memory write signal Swr are supplied, latch circuits 21 and 22 are driven th...

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Bibliographische Detailangaben
1. Verfasser: KIUCHI TETSUO
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:PURPOSE:To extend memory addresses by using independently part or the whole of a data signal or in combination with an address signal as a new address signal and accessing a memory. CONSTITUTION:When an I/O signal Sio and a memory write signal Swr are supplied, latch circuits 21 and 22 are driven through an AND gate 7 and an address of a data ROM 3 is specified by an address and data supplied through buses 4 and 5'. An address decoding signal Sad is generated by an address decoder 6 on the basis of the address and data and a chip selection signal Scs is then generated by using the address decoding signal together with a memory read signal Smr, using this as an output control signal. Then, data in the data ROM 3 is read in a microprocessor 1 through an address/data multiplex bus 5'.