PRODUCING CIRCUIT OF ERROR CORRECTION CODE

PURPOSE:To correct automatically an error correction code in accordance with the change of the auxiliary information when the data is written again, by providing a shift series pattern memory which delivers the error correction code for back-up, an exclusive OR and a circuit which produces and store...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KUMAGAI KAZUO, ICHII HIROSHI, KASADA TOSHIYUKI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To correct automatically an error correction code in accordance with the change of the auxiliary information when the data is written again, by providing a shift series pattern memory which delivers the error correction code for back-up, an exclusive OR and a circuit which produces and stores the error correction code. CONSTITUTION:Block numbers B0 and B1 of the auxiliary information needed for control and a flag F are sent to a multiplexer MPX6 via REG3-REG5 in a data format of a block. The MPX6 controls the output of these numbers and flag with a selection signal SEL1 and branches the output into three parts. The output to be applied to an ROM is turned into an address signal to obtain the output of the ROM. An REG10 performs calculation of an exclusive OR together with an EOR11 with each change of the flag byte F and corrects the storage contents of the REG10 to feed them to an EOR8. The input of an EOR9 is corrected with each change of the flag byte F with the output of an REG12.