JPS5951749B

PURPOSE:To reduce the variation of a substrate bias voltage even when power supply voltage and substrate bias current are altered by retaining the negative voltage value of a node forming a circuit constant when the bias voltage is applied to a silicon substrate forming a MOS IC. CONSTITUTION:A bias...

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Hauptverfasser:	NOZAKI SHIGEKI, EMOTO SEIJI
Format:	Patent
Sprache:	eng
Schlagworte:	AMPLIFIERS BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY CONTROLLING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS REGULATING SEMICONDUCTOR DEVICES STATIC STORES SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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creator	NOZAKI SHIGEKI EMOTO SEIJI
description	PURPOSE:To reduce the variation of a substrate bias voltage even when power supply voltage and substrate bias current are altered by retaining the negative voltage value of a node forming a circuit constant when the bias voltage is applied to a silicon substrate forming a MOS IC. CONSTITUTION:A bias generator circuit is provided in an IC chip, and bias voltage is internally applied to a substrate to thereby simplify the MOS IC device. This bias generator circuits consists of an oscillator 1, transistors Q1-Q3, a diode D1, a coupling capacitor C1, a bypass capacitor C2, transistors Q11-Q15 and nodes N3-N5. The circuit is thus constructed, and timing signals VA-VC are applied to the transistors to thereby selectively shut off or conduct the transistors Q11-Q15 so as to set the negative voltage of the node N2 driven by the oscillator 1 through the capacitor C1 constant. Then, the voltage is picked up as the substrate bias voltage VBB through the transistor Q4 and is applied to the MOS IC.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS5951749BB2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS5951749BB2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS5951749BB23</originalsourceid><addsrcrecordid>eNrjZOD2Cgg2tTQ1NDexdOJhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFIOpyMjIlSBACKOByN</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>JPS5951749B</title><source>esp@cenet</source><creator>NOZAKI SHIGEKI ; EMOTO SEIJI</creator><creatorcontrib>NOZAKI SHIGEKI ; EMOTO SEIJI</creatorcontrib><description>PURPOSE:To reduce the variation of a substrate bias voltage even when power supply voltage and substrate bias current are altered by retaining the negative voltage value of a node forming a circuit constant when the bias voltage is applied to a silicon substrate forming a MOS IC. CONSTITUTION:A bias generator circuit is provided in an IC chip, and bias voltage is internally applied to a substrate to thereby simplify the MOS IC device. This bias generator circuits consists of an oscillator 1, transistors Q1-Q3, a diode D1, a coupling capacitor C1, a bypass capacitor C2, transistors Q11-Q15 and nodes N3-N5. The circuit is thus constructed, and timing signals VA-VC are applied to the transistors to thereby selectively shut off or conduct the transistors Q11-Q15 so as to set the negative voltage of the node N2 driven by the oscillator 1 through the capacitor C1 constant. Then, the voltage is picked up as the substrate bias voltage VBB through the transistor Q4 and is applied to the MOS IC.</description><language>eng</language><subject>AMPLIFIERS ; BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; CONTROLLING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; REGULATING ; SEMICONDUCTOR DEVICES ; STATIC STORES ; SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</subject><creationdate>1984</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19841215&DB=EPODOC&CC=JP&NR=S5951749B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19841215&DB=EPODOC&CC=JP&NR=S5951749B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NOZAKI SHIGEKI</creatorcontrib><creatorcontrib>EMOTO SEIJI</creatorcontrib><title>JPS5951749B</title><description>PURPOSE:To reduce the variation of a substrate bias voltage even when power supply voltage and substrate bias current are altered by retaining the negative voltage value of a node forming a circuit constant when the bias voltage is applied to a silicon substrate forming a MOS IC. CONSTITUTION:A bias generator circuit is provided in an IC chip, and bias voltage is internally applied to a substrate to thereby simplify the MOS IC device. This bias generator circuits consists of an oscillator 1, transistors Q1-Q3, a diode D1, a coupling capacitor C1, a bypass capacitor C2, transistors Q11-Q15 and nodes N3-N5. The circuit is thus constructed, and timing signals VA-VC are applied to the transistors to thereby selectively shut off or conduct the transistors Q11-Q15 so as to set the negative voltage of the node N2 driven by the oscillator 1 through the capacitor C1 constant. Then, the voltage is picked up as the substrate bias voltage VBB through the transistor Q4 and is applied to the MOS IC.</description><subject>AMPLIFIERS</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CONTROLLING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>REGULATING</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><subject>SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1984</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD2Cgg2tTQ1NDexdOJhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFIOpyMjIlSBACKOByN</recordid><startdate>19841215</startdate><enddate>19841215</enddate><creator>NOZAKI SHIGEKI</creator><creator>EMOTO SEIJI</creator><scope>EVB</scope></search><sort><creationdate>19841215</creationdate><title>JPS5951749B</title><author>NOZAKI SHIGEKI ; EMOTO SEIJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS5951749BB23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1984</creationdate><topic>AMPLIFIERS</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CONTROLLING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>REGULATING</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><topic>SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</topic><toplevel>online_resources</toplevel><creatorcontrib>NOZAKI SHIGEKI</creatorcontrib><creatorcontrib>EMOTO SEIJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NOZAKI SHIGEKI</au><au>EMOTO SEIJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>JPS5951749B</title><date>1984-12-15</date><risdate>1984</risdate><abstract>PURPOSE:To reduce the variation of a substrate bias voltage even when power supply voltage and substrate bias current are altered by retaining the negative voltage value of a node forming a circuit constant when the bias voltage is applied to a silicon substrate forming a MOS IC. CONSTITUTION:A bias generator circuit is provided in an IC chip, and bias voltage is internally applied to a substrate to thereby simplify the MOS IC device. This bias generator circuits consists of an oscillator 1, transistors Q1-Q3, a diode D1, a coupling capacitor C1, a bypass capacitor C2, transistors Q11-Q15 and nodes N3-N5. The circuit is thus constructed, and timing signals VA-VC are applied to the transistors to thereby selectively shut off or conduct the transistors Q11-Q15 so as to set the negative voltage of the node N2 driven by the oscillator 1 through the capacitor C1 constant. Then, the voltage is picked up as the substrate bias voltage VBB through the transistor Q4 and is applied to the MOS IC.</abstract><oa>free_for_read</oa></addata></record>
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subjects	AMPLIFIERS BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY CONTROLLING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS REGULATING SEMICONDUCTOR DEVICES STATIC STORES SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
title	JPS5951749B
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