JPS5951749B

PURPOSE:To reduce the variation of a substrate bias voltage even when power supply voltage and substrate bias current are altered by retaining the negative voltage value of a node forming a circuit constant when the bias voltage is applied to a silicon substrate forming a MOS IC. CONSTITUTION:A bias generator circuit is provided in an IC chip, and bias voltage is internally applied to a substrate to thereby simplify the MOS IC device. This bias generator circuits consists of an oscillator 1, transistors Q1-Q3, a diode D1, a coupling capacitor C1, a bypass capacitor C2, transistors Q11-Q15 and nodes N3-N5. The circuit is thus constructed, and timing signals VA-VC are applied to the transistors to thereby selectively shut off or conduct the transistors Q11-Q15 so as to set the negative voltage of the node N2 driven by the oscillator 1 through the capacitor C1 constant. Then, the voltage is picked up as the substrate bias voltage VBB through the transistor Q4 and is applied to the MOS IC.