MEMORY CONTROLLING METHOD

PURPOSE:To decrease the number of memory elements, by using a memory element which has large capacity in an address direction to constitute a memory which has capacity less than the capacity in the address direction of the memory element. CONSTITUTION:The output data bus signal of a CPU20 is written in a parallel- serial converter 27, whose output WD is written in an address indicated by a memory 21. Then, a count-up signal CUP is outputted from a timing generation part 24 to an external address generation part 25 to advance an external address by one, and the output WD of the converter 27 is written in the address. Thus, the timing generation part 24 applies the signal CUP to the external address generation part 25 to advance the external address signal, one by one, and a shift signal SHP is applied to the converter 27 to change the output WD into contents which are one-bit higher in order, writing them in the memory 21. Then, this is repeated until the final contents of the data bus signal of the CPU20 are written in the memory 21. In reading operation, output data RD from the memory 21 is fetched in a serial-parallel converter 28.