PLL SYSTEM DIGITAL FREQUENCY SYNTHESIZER

PURPOSE:To vary an output frequency in a minute step without decreasing a phase comparison frequency than a frequency of a voltage controlled oscillator by forming a reference phase comparison frequency with a frequency divider having a rational number and a fixed frequency divider and dividing the frequency of the VCO by a frequency divider having the same frequency dividing ratio of the fixed frequency divider so as to form a feedback phase comparison frequency. CONSTITUTION:A frequency dividing circuit 6 is constituted by the cascade connection of a bit rate multiplier and its frequency dividing ratio is L/K (where; K and L are integral numbers). An output frequency of the frequency dividing circuit 6 becomes FXK/L, it is further frequency-divided by M at the fixed frequency divider 7 and its output frequency F K/L M is inputted to a reference input terminal A of the phase comparator 2. On the other hand, a value f/M where the oscillating frequency (f) of the voltage controlled oscillator VCO4 is divided by a frequency divider 8 having a frequency dividing ratio of M is inputted to a feedback input terminal B of the comparator 2. The comparator 2 compares the phase of both of the said inputs, its compared output becomes a control voltage Vd via an LPF3 so as to control the oscillating frequency (f) of the VCO4. Thus, a frequency of K F/L is outputted from a terminal OUT by controlling the oscillating frequency of the VCO4 so that the phase difference to the two input terminals A, B to the phase comparator 2 is zeroed.