INFORMATION TRANSFER SYSTEM

PURPOSE:To attain the reduction in signal lines by using a data signal line and a clock signal line in common in a simple type information transfer circuit. CONSTITUTION:When a clock signal is applied to a drive control circuit CONT of a master device MAIN, the device controls a signal so as to be outputted with a signal level (b) opposite to a signal level (a) superposed on a signal line to drive circuits 1, 2. This level change is detected by a level detecting circuit LEV at a slave device SUB so as to bring the level (a) of the drive circuit 2 into the same level (b). Then the master device MAIN brings the drive circuit 1 into off-state after a certain time is elapsed, and the output is obtained by the drive circuit 2 only. The drive circuit 1 of the slave device SUB inverts a signal line after a prescribed time from this change point when a data is at ''1''. The master device MAIN detects it, a data reproducing circuit DPR reproduces the data and the drive circuit 2 is brought into the state of signal line.