HIERARCHICAL ARITHMETIC SYSTEM

PURPOSE:To increase the processing speed for an address conflict, a BC instruction by using master and slave arithmetic devices and shortening the arithmetic cycle of the slave arithmetic device compared with that of the master arithmetic device. CONSTITUTION:A master arithmetic device containing the 1st arithmetic execution unit 20A and a slave arithmetic device including the 2nd arithmetic execution unit 20B can process instructions in a 2-cycle pitch and a 1-cycle pitch, respectively. At the same time, the whole unit is synchronized with use of a timing pulse of the 1-cycle pitch and the width of various control signals are all constituted as one cycle. Therefore the arithmetic end signal of the master arithmetic device is kept on for a cycle per generation and then turned off for the next one cycle. The unit 20B can obtain an arithmetic result more quickly than the unit 20A even with a program which is mostly occupied by instructions of arithmetic stages such as load, add, etc. like a system program. This increases the processing speed for an address conflict and a BC instruction.