SYNCHRONIZING CIRCUIT

PURPOSE:To prevent a ringing phenomenon and to accelerate the synchronization by changing the input signal to be applied to a flip-flop of a synchronizing circuit with the given clock signal. CONSTITUTION:An AND circuit 4 uses an inverted signal Q, a non-synchronizing signal I and a clock signal CL...

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1. Verfasser: KURIHARA SADAO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To prevent a ringing phenomenon and to accelerate the synchronization by changing the input signal to be applied to a flip-flop of a synchronizing circuit with the given clock signal. CONSTITUTION:An AND circuit 4 uses an inverted signal Q, a non-synchronizing signal I and a clock signal CL of an FF7 as inputs and therefore delivers an output to an OR circuit 6 when the FF7 is reset together with signals CL and I set at 1, respectively. Then the circuit 4 produces a clock signal CLK and inverts the FF7 to set it. An AND circuit 5 is actuated when the FF7 is set and delivers an output to the circuit 6 when signals I and CL are set at 0 and 1, respectively. Then the circuit 5 delivers the signal CLK to the FF7 to invert and reset the FF7. Therefore the cycle of the clock CL can be set at the time obtained by adding the effective time of the pulse width to the element delay, thereby accelerating the synchronization.