MANUFACTURE OF SEMICONDUCTOR DEVICE

PURPOSE:To realize an MNOS gate structure having electrically stabilized characteristics by a method wherein no hysteresis is generated in the C-VG characteristics by performing an annealing treatment two times. CONSTITUTION:A gate oxide film 22 and a silicon nitriding film 23 are formed on a silico...

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Hauptverfasser: KURIHARA HIROYUKI, KIYOZUMI FUMIO, ABE HIDEJI
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creator KURIHARA HIROYUKI
KIYOZUMI FUMIO
ABE HIDEJI
description PURPOSE:To realize an MNOS gate structure having electrically stabilized characteristics by a method wherein no hysteresis is generated in the C-VG characteristics by performing an annealing treatment two times. CONSTITUTION:A gate oxide film 22 and a silicon nitriding film 23 are formed on a silicon semiconductor substrate 21 and an annealing treatment is performed in the atmosphere of dry nitrogen or oxygen. A polycrystalline silicon film 24 is formed and the silicon film 24 is patterned in a form to become a gate along with the silicon nitriding film 23 and the gate oxide film 22 and is performed an annealing treatment in the atmosphere of dry oxygen and, following that, in the atmosphere of dry nitrogen.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS59181574A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS59181574A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS59181574A3</originalsourceid><addsrcrecordid>eNrjZFD2dfQLdXN0DgkNclXwd1MIdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcGmloYWhqbmJo7GxKgBAG6vIzE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>KURIHARA HIROYUKI ; KIYOZUMI FUMIO ; ABE HIDEJI</creator><creatorcontrib>KURIHARA HIROYUKI ; KIYOZUMI FUMIO ; ABE HIDEJI</creatorcontrib><description>PURPOSE:To realize an MNOS gate structure having electrically stabilized characteristics by a method wherein no hysteresis is generated in the C-VG characteristics by performing an annealing treatment two times. CONSTITUTION:A gate oxide film 22 and a silicon nitriding film 23 are formed on a silicon semiconductor substrate 21 and an annealing treatment is performed in the atmosphere of dry nitrogen or oxygen. A polycrystalline silicon film 24 is formed and the silicon film 24 is patterned in a form to become a gate along with the silicon nitriding film 23 and the gate oxide film 22 and is performed an annealing treatment in the atmosphere of dry oxygen and, following that, in the atmosphere of dry nitrogen.</description><edition>3</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1984</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19841016&amp;DB=EPODOC&amp;CC=JP&amp;NR=S59181574A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19841016&amp;DB=EPODOC&amp;CC=JP&amp;NR=S59181574A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KURIHARA HIROYUKI</creatorcontrib><creatorcontrib>KIYOZUMI FUMIO</creatorcontrib><creatorcontrib>ABE HIDEJI</creatorcontrib><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><description>PURPOSE:To realize an MNOS gate structure having electrically stabilized characteristics by a method wherein no hysteresis is generated in the C-VG characteristics by performing an annealing treatment two times. CONSTITUTION:A gate oxide film 22 and a silicon nitriding film 23 are formed on a silicon semiconductor substrate 21 and an annealing treatment is performed in the atmosphere of dry nitrogen or oxygen. A polycrystalline silicon film 24 is formed and the silicon film 24 is patterned in a form to become a gate along with the silicon nitriding film 23 and the gate oxide film 22 and is performed an annealing treatment in the atmosphere of dry oxygen and, following that, in the atmosphere of dry nitrogen.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1984</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD2dfQLdXN0DgkNclXwd1MIdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcGmloYWhqbmJo7GxKgBAG6vIzE</recordid><startdate>19841016</startdate><enddate>19841016</enddate><creator>KURIHARA HIROYUKI</creator><creator>KIYOZUMI FUMIO</creator><creator>ABE HIDEJI</creator><scope>EVB</scope></search><sort><creationdate>19841016</creationdate><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><author>KURIHARA HIROYUKI ; KIYOZUMI FUMIO ; ABE HIDEJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS59181574A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1984</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KURIHARA HIROYUKI</creatorcontrib><creatorcontrib>KIYOZUMI FUMIO</creatorcontrib><creatorcontrib>ABE HIDEJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KURIHARA HIROYUKI</au><au>KIYOZUMI FUMIO</au><au>ABE HIDEJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><date>1984-10-16</date><risdate>1984</risdate><abstract>PURPOSE:To realize an MNOS gate structure having electrically stabilized characteristics by a method wherein no hysteresis is generated in the C-VG characteristics by performing an annealing treatment two times. CONSTITUTION:A gate oxide film 22 and a silicon nitriding film 23 are formed on a silicon semiconductor substrate 21 and an annealing treatment is performed in the atmosphere of dry nitrogen or oxygen. A polycrystalline silicon film 24 is formed and the silicon film 24 is patterned in a form to become a gate along with the silicon nitriding film 23 and the gate oxide film 22 and is performed an annealing treatment in the atmosphere of dry oxygen and, following that, in the atmosphere of dry nitrogen.</abstract><edition>3</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title MANUFACTURE OF SEMICONDUCTOR DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T19%3A54%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KURIHARA%20HIROYUKI&rft.date=1984-10-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS59181574A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true