PROCESSOR CONTROLLING SYSTEM

PURPOSE:To simplify the constitution of a circuit by connecting one master processor and plural slave processors to one set of common bus, sending out a maintenance packet from the master processor, and selecting the slave processor. CONSTITUTION:When a master processor 1 controls a slave processor...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: TOBE YOSHIHARU, NISHIWAKI MINEO, YASHIRO ZENICHI, KUNIYOSHI SHIYUUICHI
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:PURPOSE:To simplify the constitution of a circuit by connecting one master processor and plural slave processors to one set of common bus, sending out a maintenance packet from the master processor, and selecting the slave processor. CONSTITUTION:When a master processor 1 controls a slave processor 2, in accordance with an instruction of the master processor 1, a bus interface circuit of the master processor 1 generates a maintenance packet containing a processor number of the slave processor to be controlled, and a command and sends it out to a system bus 5. The bus interface circuit 3 of the slave processor 2 receives the maintenance packet from the system bus 5, and when a processor number contained in said packet coincides with its own number, a command code is decoded, and the slave processor 2 is controlled through a control line 7. In this way, the constitution of a circuit is simplified, and the slave processors are extended easily.