ADDRESS DECODER CIRCUIT

PURPOSE:To reduce remarkably power consumption, by inserting a capacitor between a common contact of the 1st circuit turning off only when selected and the 2nd circuit turning on only when turned on, and a supply terminal of a clock signal. CONSTITUTION:FET.T00-T03, T10-T13...T150-T153 constitute respectively the 1st circuits B0, B1...B15. FET.T04-T07, T14-T17...T154-T157 are connected in sereis to constitute the 2nd circuits D0, D1...D15. Further, capacitors C0, C1... C15 are inserted between common connecting points K0, K1...K15 and a supply terminal 2 of the clock signal. When address signals A0-A3 are all 0 and an NOR gate circuit G0 is selected alternatively, a current flowing to the NOR gate circuit G0 is only the charge/discharge current of the capacitor C0 except a current applied to an access line l0. On the other hand, the current flowing to NOR gate circuits G1-G15 is the charge/discharge current only to the capacitors C1, C2...C15 every time the clock signal CLK changes as 1, 0 during this time. Thus, the power consumption is reduced with the NOR gate circuits G0-G15 by selecting the capacitors C0-C15 to small values.