SEMICONDUCTOR STORAGE DEVICE

PURPOSE:To improve the access speed of a semiconductor storage device, by generating a timing signal to a control circuit of a column address buffer in a specified small delay time. CONSTITUTION:A timing signal S1 from a row address clock generator 10 is inputted to a column address clock generator 14, and after the operation of the row system, the column system is operated. Timing signals S3, S2 to a column address buffer 16 and its control circuit 26 are generated earilier than the signal S1 via a buffer control circuit 24, then the signal S2 is gnerated in a smaller delay time than the minimum delay time of a column strobe signal CAS to a row strobe signal RAS. Thus, the column system address buffer is made operative earlier than the column system clock generator, the time required for access is reduced, the cycle time is made small and the access speed is improved.