MEMORY COMMON SYSTEM

PURPOSE:To improve processing capability, by executing a time division control of a common memory in synchronizing with operation of a CPU having priority CPU, and forcibly assigning the following state in case when sending and receiving a data is requested from the CPU having priority. CONSTITUTION:By synchronizing with a basic operation clock of a CPU 91 having priority, a state is assigned in order to CPUs 91-94. Also, when an access request from the CPU 91 is detected, the following state is assigned to the CPU 91 by a synchronization controlling circuit 50 incorporated in a time division control part 5. A variation point of a time division state is an alternative point of time to access from each CPU 91-94, and to a common memory 4, access from any CPU is allowed. Accordingly, even if the circuit 50 suddenly assigns the following state to the CPU 91, no influence is exerted on operation of other CPUs, and an internal request of the CPU 91 can be all processed without a waiting time.