MULTI-ARRAY PROCESSOR

PURPOSE:To execute a serial transfer between optional cntinous unit processors and a peripheral device at a high speed and efficiently, by selectively controlling setting of a data or storage of a data to a transfer register in an optional unit processor. CONSTITUTION:When a data of the N-th unit processor is teansferred to a peripheral device 2, control signals of an H level from a switch control signal input terminal 10N of an NAND gate 8, and of an L level from control input terminals 101-10N-1 are inputted to each gate 8. Accordingly, only a gate 8N is opened, other gates 8 are clsed, and a data of a transfer register 3N of the N-th unit processor is transferred to the peripheral device 2 through a bypass line 6. That is to say, a data of a transfer register of an optional unit processor is transferred to the peripheral device 2 through the shortest transfer line that has been formed, without passing through a transfer register of the preceding unit processor.